1. Field of the Invention
The present invention relates to a planarization apparatus for planarizing a coating film on a substrate before the coating film is hardened.
2. Description of the Related Art
In a process of forming, for example, a multilayer wiring structure of a semiconductor integrated circuit or the like, processing of forming an insulating film between metal wirings on a wafer is performed. For the processing of forming the insulating film, for example, a coating method is widely used which is a so-called spin-coating of supplying a liquid insulating film material onto the wafer, and rotating the wafer to diffuse the insulating film material over the wafer front surface to thereby apply an insulating film on the wafer. When the insulating film is applied on the wafer, a hardening processing of hardening the insulating film under a high temperature is then performed to finally form the insulating film. The SOG (Spin On Glass) film or SOD (Spin On Dielectric) film which is common as the insulating film is formed as described above.
However, since the amount of the insulating film material entering the depressed portions varies due to the depth of steps and roughness of a base pattern when using the above-described coating method, projections and depressions may be formed on the front surface of the formed insulating film. Once the projections and depressions are formed on the front surface of the insulating film, focus is not partially achieved on the resist film at the upper layer at the time of exposure of the photolithography step, resulting in non-uniformity in the line width of the resist pattern. This also causes non-uniformity in the width of the etched trenches in the insulating film. Further, the depth of the etched trench also differs between a portion with a large thickness and a portion with a small thickness of the insulating film. If the width and the depth of the etched trench in the insulating film varies as described above, the metal wiring embedded in the trench in the insulating film differs in length and thickness, leading to non-uniformity in electric resistance of the wirings within the wafer.
Thus, the formation of the projections and depressions on the front surface of the insulating film causes various troubles in the process of forming the multilayer wiring structure and the finally formed multi-layer wiring structure.
Hence, when the insulating film is formed by the above-described coating method, the CMP (Chemical Mechanical Polishing) processing to planarize the insulating film is conventionally performed after the insulating film is hardened. The CMP processing is performed by bringing a polishing pad into contact with the wafer front surface while supplying a liquid slurry containing silica particles (a polishing liquid) to polish the wafer front surface in the CMP apparatus (Japanese Patent Application Laid-open No. 2004-106084).
However, the above-described CMP apparatus employs a polishing pad twice or larger than the wafer, and therefore is very large in size and also consumes a large amount of power. In addition, the apparatus requires use of a large amount of expensive slurry, leading to increased running cost. Furthermore, if the slurry remains on the wafer, it can contaminate or scratch the multilayer wirings. Therefore, a cleaning step performed by a dedicated cleaning unit for washing away the slurry is separately required, resulting in an increase in the number of processing steps and complexity.